As we close out 2008, I would like to thank our customers and partners for making the year our most successful ever. Our recipe for success continues to be business innovation that benefits everyone. As we head into a tumultuous 2009, one thing is certain: Innovation is a winner’s game.

Our business partners have worked closely with us over the last year to monetize their valuable assets in new and creative ways to maximize the value of their assets for their companies. Our licensing customers have been able to incorporate this famous IP into their products to create new, differentiated applications at a low-cost and low-risk. We are proud and honored to have the privilege to stand in the middle and facilitate your success.

Heading into 2009, you can expect to see new and exciting announcements as we continue to push the envelope of business innovation for the semiconductor community.

President and CEO

Blogs

Design-Reuse.com: Beware the Unflatteners

In Thomas Friedman’s now famous “The World is Flat” book published in 2005, Friedman describes how the world economy has become “flattened”. Fueled by technology, lowered trade barriers, nearly all leading edge companies are now multinational and borders are almost virtual. >>More

ElectronicsWeekly.com: Back to the Future

In the United States we see today the imminent death of the once mighty automobile industry.

General Motors is unlikely to survive the next months without government intervention and a surprisingly large number of Americans are just fine with that. The sad facts are that aside from the economic carnage that a collapse of GM would have on the American economy, nobody really cares whether this company survives. >>More

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Webinar: Next Generation Test and Debug Solutions

cJTAG – IEEE 1149.7 is the first semiconductor IP solution to implement the new IEEE 1149.7 test and debug standard. The IP core was developed by Texas Instruments and packaged, distributed and supported by IPextreme. IEEE 1149.7 does not change or replace IEEE 1149.1. Instead, it offers a scalable set of extensions to the IEEE 1149.1. Some of the advantages of the new IEEE 1149.7 standard are that it requires fewer pins, adds power management and powerful new debug features while maintaining full compatibility with existing IEEE 1149.1 based hardware and software.

This webinar which will feature Stephen Lau (Texas Insturments), Pierre - Xavier Thomas and Rick Tomihiro (IPextreme), will cover the new IEEE 1149.7 standard and the robust set of features available in the cJTAG – IEEE 1149.7 IP core. Join us as we discuss how the cJTAG – IEEE 1149.7 IP core can be utilized in your next chip design.

Nascent 1149.7 complements venerable 1149.1 JTAG
By Adam Ley Chief Technologist – Boundary Scan
ASSET InterTech

The draft, but soon to be ratified, 1149.7 test and debug standard builds on and extends the test and debug capabilities of the original 1149.1 boundary scan/JTAG standard. For many good reasons, 1149.7 maintains backward compatibility with 1149.1 and, at the same time, incorporates test and debug capabilities not found in 1149.1.

While 1149.7 was launched primarily as a debug initiative, the working group has gone to considerable lengths to ensure that the test legacy of the original 1149.1 is retained. Notable among 1149.7’s test-related provisions are the specification of scan selection directives that ensure update, capture and run-test synchronization, the definition of suitable extensions to the boundary-scan description language (BSDL), and the definition of a hierarchical scan description language (HSDL) to accommodate multi-die packages.

As a minimum, 1149.7 is a two-wire test and debug interface instead of the minimum four-wire interface defined in 1149.1. In addition, 1149.7 enables certain architectural features that are well suited to testing and debugging advanced multi-core and/ or multi-die component packages, such as System-on-Chip (SoC), System-in-Package (SiP), Package-on-Package (PoP), and Multi-Chip Module (MCM).

How 1149.7 Works

1149.7 retains full compatibility with 1149.1 by implementing a link or adapter layer that connects 1149.7 to 1149.1. By doing so, 1149.7 builds on the rather extensive infrastructure of 1149.1 technology already deployed in chips, on circuit boards and in systems. In addition, 1149.1 boundary-scan tool systems, such as ASSET’s industry-leading ScanWorks platform with its embedded instrumentation capabilities, are inherently compatible with 1149.7, although specific support for 1149.7 will need to be implemented.

Figure 1 illustrates how 1149.7 wraps an adapter layer around the 1149.1 capabilities that have been embedded into chips. The manner in which this is done maintains compatibility between 1149.7 and 1149.1 components where both are present on circuit boards or in systems.

Figure 1

Enhancing Multi-core/Multi-die Validation, Test, and Debug

The 1149.1 standard includes a minimum of four signals, two of which – Test Data In (TDI) and Test Data Out (TDO) – form a serial daisy chain which typically connects multiple chips on a circuit board. 1149.7 reduces the minimum number of signals from 1149.1’s four to just two. By eliminating the TDI and TDO signals, the 1149.7 standard eliminates the requirement in the 1149.1 standard whereby TDI and TDO must be connected in a serial daisy chain. By doing so, an 1149.7 implementation is not limited to serial daisy-chain architectures. Instead, a star architecture can be configured. This can be particularly effective when it comes to validating, testing and debugging devices made up of multiple cores or die, such as SoC, SiP, PoP and MCM packages.

For example, a SiP device might be comprised of three die. Each die’s embedded TAP controller would be connected to its own 1149.7 TAP and thence in common to the package’s one TAP interface to the outside world. (Figure 2) Daisy chaining multiple die in a package can lead to an implementation that is not compliant with the 1149.1standard.

Figure 2

Bridging to Embedded Instrumentation

1149.7’s provisions for multi-core and multi-die architectures complement quite effectively the capabilities being defined in the preliminary IEEE P1687 Internal JTAG (IJTAG) standard for embedded instruments in chips. The P1687 IJTAG standard specifies the interface to embedded instruments as well as some of the mechanisms for managing them.

An increasing number of embedded instruments from chip manufacturers and intellectual property (IP) providers are being incorporated into chips because some of the traditional validation, test and debug technologies are becoming inadequate. As the speeds of chips and serial interconnect buses accelerates beyond five gigabits per second (Gbps), as the physical access needed to probe device pins and test pads on circuit boards disappears, and as the overall complexity of electronic systems increases, traditional technologies like oscilloscopes and logic analyzers as well as production test technologies such as in-circuit test (ICT) are becoming increasingly challenged.

A major advantage of an open industry standard like P1687 is the fact that cost-effective third-party tools typically become available to support the standard. ASSET has already announced its commitment to supporting P1687. As a result, ScanWorks is the leading platform for automating, accessing and analyzing embedded instrumentation.

More information on the IEEE P1687 IJTAG standard can be found on the working group’s web page at http://grouper.ieee.org/groups/1687/ or in a recent article in ASSET’s Connect e-newsletter at http://www.asset-intertech.com/connect/2007Q3/ijtag_update.htm.

On a Solid Foundation

The wisdom of the 1149.7 working group’s strategy of basing this new standard on the solid foundation of 1149.1 will be demonstrated over time. One of the hurdles any standard always faces is adoption by the industry. But unlike other new standards, 1149.7 already has a presence in the marketplace thanks to its ancestor, 1149.1. In addition, 1149.7 will be able to take advantage of the significant infrastructure that has grown up around 1149.1. As a result, momentum for 1149.7’s adoption is already present in the marketplace.

www.asset-intertech.com

Product: MCF5227X V2 Microcontroller with Touchscreen

Freescale’s MCF5227x ColdFire microprocessor family is the ideal device for developers looking to add more control options to their consumer or industrial applications. Featuring an integrated LCD controller and touchscreen module, the MCF5227x family is designed to provide an easy way to add support for graphical LCD interfaces to industrial system.
>> More on Freescale MCF5227x

About V2 ColdFire® Processor IP

The V2 ColdFire Core is one of the smallest 32-bit processors available today while still providing industry leading performance. Freescale MCF52xx devices built from the V2 ColdFire Core can be found in health care instrumentation, point-of-sale terminals, factory automation, fire and security systems, and many other industrial and consumer applications.
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Product: Infineon TC1767

The TC1767 is the value optimized member of the AUDO FUTURE product family designed for automotive applications. Its 80/133Mhz award-winning TriCore® CPU provides high-end microcontroller performance combined with sophisticated DSP capabilities.
>> More Infineon TC1767

About TriCore Microcontroller IP

The TriCore IP from IPextreme is the first unified MCU-DSP architecture in a single core. Ideally suited to SoC applications that require both microcontroller and DSP functionality together with high performance, low cost and minimal power consumption, TriCore meets the needs of automotive, industrial, mass storage and communications applications where TriCore based ASSP silicon devices from Infineon are already successful.
>> More on TriCore Microcontroller IP

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V1 ColdFire Processor

DesignCon 2009
IPextreme Tutorial:
CoReUse/QCore - Industries First Design Reuse Methodology with Compliance Checking Tool
Monday, Feb 2, 1:30 - 4:30 pm
Booth#: 841
Register Here

February 2 - 5, 2009

SNUG Vendor Fair

March 17, 2009