The first half of 2008 has been a busy time for us at IPextreme® with the launch of two important innovations for the semiconductor community.  We thank our customers who have embraced our revolutionary Core Store™ which brings the highest quality IP to them at the lowest price with the simplest licensing transaction in the IP industry.

In April, IPextreme pushed the envelope again with the announcement we'd be opening up NXP's secret sauce for IP creation, the CoReUse™ standard, for licensing in the form of inexpensive e-books that could be purchased from the Core Store. I'd like to draw your attention to two contributed articles from our EDA partners Atrenta® and Forte Design Systems around the topic of how valuable tools from these companies can help contribute to successful IP design at your company.

President and CEO

Blogs

Design & Reuse On Cores: IP Urban Legends

Stop me if you heard this one before. An engineering manager tells you a horror story of purchasing an IP core purely on the basis of price. Engineering wanted the other more expensive solution, but management instructed them to go with the cheapest solution. More

ElectronicsWeekly.com: On Waiting for Godot

In this most celebrated play of the 20th century, two tramps patiently wait by a tree for days for someone named Godot to arrive, making excuses for idleness ("nothing to do") while they wait. Not even sure what Godot will do for them when he arrives, they continue to wait, anticipate, reflect, argue, dream, and wait some more. Of course, Godot never arrives. More

Introduction to CoReUse
by Ralph von Vignau of NXP

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CoReUse represents more than a decade and a 100 man years of investment by NXP to develop a comprehensive, practical, and efficient system that can be deployed at the group and enterprise level for engineers to develop reusable, high quality IP. It is in use today by nearly every NXP design group worldwide as the standard by which IP is developed and shared across the company and as qualification for all IP purchases.

Join Ralph in this three part presentation on the motivation behind CoReUse as well as the benefits NXP engineers receive from adopting this methodology.

The entire library of CoReUse eBooks are now available for purchase through IPextreme. Visit our Core Store to browse our selection.

Ensure high-quality IP with Atrenta’s SpyGlass® family
By Piyush Sancheti, Sr. Director of Business Development, Atrenta Inc.

While semiconductor intellectual property (IP) reuse accelerates system on chip (SoC) design and improves overall productivity, it also creates unique challenges. Since the IP supplier and consumer are usually separated, both need reliable methods for qualifying and certifying IP for the general market and for the target SoC, respectively. To complicate matters further the overall quality of the IP has a huge impact on the SoC project and the team’s ability to meet the target objectives of the application. Often, poor choices made during IP design, selection or integration result in designs that are very difficult to implement and pose significant design closure challenges for the downstream implementation (synthesis and layout) flow.

Atrenta’s industry-standard SpyGlass® is a comprehensive solution for Early Design Closure®. IP suppliers can use SpyGlass to verify and optimize RTL during IP development and packaging. IP consumers, on the other hand, can use the same tools to ensure the quality of incoming IP and smooth integration into the SoC. SpyGlass addresses several key design aspects like compliance to coding guidelines, synthesizability, simulation-readiness, clock domain crossings, timing constraints, timing exceptions and power at RTL, before committing to implementation. To ensure efficient use of its solution Atrenta also provides GuideWare™, a set of pre-packaged methodologies targeted at different stages of design/IP creation, IP acceptance, and SoC integration. Atrenta has also recently launched its SpyLinks™ industry partnerships program to collaborate with key players in the semiconductor supply chain to maximize the benefits of Atrenta’s solutions.

As a SpyLinks member, IPextreme has standardized on the Atrenta SpyGlass platform and GuideWare methodology for IP inspection and certification. The goal is to ensure quality, completeness and ease of integration for IPextreme’s end customers. IPextreme also plans to supply SpyGlass setup information for its IP to customers to enable easier adoption of SpyGlass at the SoC level.

For more information on Atrenta, please visit www.atrenta.com or email spylinks@atrenta.com

High-level Synthesis and IP Reuse with Cynthesizer™
By Mike Meredith, VP Technical Marketing, Forte Design Systems

Forte is pleased that the results achieved using its Cynthesizer™ product for high-level SystemC synthesis merited its inclusion as the basis of the NXP CoReUse recommended standards for behavioral synthesis that have just been made available to the public by NXP and IPextreme. 

The CoReUse guides describe NXP’s IP reuse tools methodology and represent a detailed, practical collection of best practices that have been proven in use at Philips Semiconductor and NXP over the last 10 years. They cover a broad range of topics from naming conventions and IP deliverables to DFT and verification standards as well as system-level design, transaction-level modeling, and high-level synthesis.  It is a remarkably comprehensive set of reuse techniques.

Reuse-oriented users will be interested in the new scope of reuse made possible by high-level synthesis using Cynthesizer. With Cynthesizer, the module behavior is described as a combination of untimed behavioral code along with cycle-accurate, pin-level interface code. Cynthesizer’s high-level synthesis process schedules the required operations to satisfy the protocol timing along with user-defined latency and other constraints. Cynthesizer uses detailed knowledge of the .lib file for the user’s chosen process technology and clock frequency, ensuring that it never creates combinatorial paths that will make it difficult to achieve timing closure.

From a reuse point of view, this automated scheduling and pipelining capability means that the algorithmic code can be written as C++ classes that are reusable — not just across a narrow range of process nodes and clock frequencies like RTL — but with virtually any process node and clock speed.   

By varying latency and other user-defined constraints, the same high-level source code can even be reused in varied products with a broad range of performance constraints, and this can be accomplished efficiently without paying an area and power penalty for unneeded performance.

Furthermore, Cynthesizer is unique in that the productivity and reuse benefits of high-level design with Cynthesizer have been successfully achieved in control-dominated production designs, such as memory controllers and I/O controllers, as well as computational designs, such as multimedia codecs.

As proliferation of high level design continues, designers looking for ways to maximize their reuse possibilities will increasingly invest their engineering effort in flexible high-level code rather than RTL and will look to tools like Cynthesizer for high-productivity design, reuse, and retargeting.

For more information on Forte Design Systems, please visit www.forteds.com

Product: MCF51AC256 32-bit Industrial Microcontroller

IP Core : V1 ColdFire® Processor

"The MCF51AC256 is part of the Flexis microcontroller series and includes complimentary families of 8-bit S08 and 32-bit V1 ColdFire microcontrollers.The Flexis series of devices includes complimentary
families of 8-bit S08 and 32-bit ColdFire® V1 microcontrollers that have a common set of peripherals and development tools to deliver
the ultimate in migration flexibility. Target applications for the MCF51AC256 include general industrial: Motor Control, Building Control, HVAC Systems, etc., and also has appliance applications: Dishwasher, Refrigerators, Washing Machines, Dryers."

More info:
V1 ColdFire Processor IP

Purchase V1 ColdFire Processor online

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Product: TC1797

IP Core:TriCore® Microcontroller

"The TC1797 is the performance optimized flagship of the AUDO FUTURE product family designed for automotive applications. Its 180MHz award-winning TriCore® CPU provides high-end microcontroller performance combined with sophisticated DSP capabilities. A dedicated peripheral control processor (PCP) manages on-chip peripherals and relieves the TriCore from standard processing tasks. On top of this, a fast interrupt response time assures low latencies and low performance overhead for interrupt driven systems. Equipped with 4MByte of embedded Flash and a total of 224KByte RAM the TC1797 is one of the highest performing devices for embedded real-time automotive applications."

More info:
TriCore Microcontroller IP

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Now Available:
Freescale ColdFire® IP
from IPextreme.

Visit the IPextreme Core Store.

Freescale V1 ColdFire Processor for Altera Cyclone III (FPGA)