Tech Tip: Multi-Core SoC Software Debugging and Performance Optimization

By Christian Lipsky, Sr. Design Engineer, IPextreme

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With MCDS, only relevant data has to be captured. MCDS brings on-chip filter capabilities, trigger logic, trace data compression and performance counters.

MCDS has the advantage of scaling with Moore’s Law and clock frequency trends. The required SoC trace bandwidth is increasing with Moore’s Law (more on-chip cores) and rising clock frequencies. MCDS is memory limited whereas trace port based technologies are bandwidth limited and gate/memory costs are decreasing at a more rapid rate than bandwidth/pin costs.

MCDS requires no extra pins, utilizes trace data compression and has an enabler for full visibility into the system. The MCDS is able to trace multiple cores in parallel and in real-time while they are running at full operating speed. Time stamps are used to sort the trace messages in the trace memory (EMEM). So trace reconstruction with a scalable granularity down to emulation clock cycle level is possible. Trace messages from different debug targets have an exact time correlation.

For further information about MCDS and other pertinent technologies, please contact us at info@ip-extreme.com