Ecosystems are quickly becoming the key differentiator for buying IP. Customers want be part of a community of users that adds value to the IP above and beyond the code. Power.org is an example of such a community, where many companies are coming together with a single-minded mission, to advance Power Architecture™ technology. IPextreme and Freescale recently announced our little corner of that ecosystem by providing the first Freescale Power Architecture microprocessor IP available for broad adoption.

President and CEO

Thursday May 24th 10:00am PDT

"Dream It, Design It, Build It – Integrating Power Architecture e200 Cores.”

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Bringing Power to the people. The Power Architecture™ e200 family of cores are fully synthesizable and implement Power ISA 2.03, making them code compatible with a huge installed base. They leverage standard technologies, such as the AMBA® bus, making them easy to integrate with other technologies. Freescale has shipped over one million zero-defect 32-bit MCUs built on these Power Architecture™ cores.

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Freescale e200 Cores:
Integration Into Embedded Solutions
by IPextreme - Pierre-Xavier Thomas

Power Architecture core IP is now more broadly available for open licensing, enabling system-on-chip (SoC) designers to leverage this flexible technology for a wide assortment of applications. Freescale‘s e200 Power Architecture core family is an example of this new industry enablement. This core family is proven in many automotive applications and is ideal for a broad range of other applications such as industrial control, medical devices, compact networking solutions, digital home solutions, avionics and robotics. The e200 family of cores has four members that span a useful price performance range. They are fully synthesizable and implement Power ISA 2.03 making them code compatible with a huge installed base. They leverage standard technologies, such as the AMBA® bus that make them easy to integrate with other technologies. These high-performance, low-power, small-footprint cores are software compatible with the extensive Power Architecture installed base and are supported by a large and growing ecosystem of development tools.

e200 cores can efficiently be integrated into embedded applications. The four cores in the e200 family range from the tiny, four-stage e200z0 core that runs the dense variable length encoding (VLE) instruction set up to 450MHz seven stage z6 cores with cache, memory management units and floating point units that also runs the full 32-bit instruction set of other Power Architecture chips. This allows SoC designers to select a core from within the family which best meets their needs today and provides compatible options for the future. For example, SoC designers can select from a cache or cacheless core, with or without MMU, a Harvard or unified AMBA 2.0 System Bus interface, and a 32 bit or 64 bit System Bus interface.

SoC designer can easily integrate the e200 cores and create memory subsystems thanks to the simple AMBA 2.0 bus cycles that these cores generate on the system bus.

Read More about the e200 core family and licensing model

Join our Webinar on e200 Integration on May 24th 10:00am PDT

Multi-Core SoC Software Debugging
and Performance Optimization
By Christian Lipsky, Sr. Design Engineer, IPextreme

Traditional debugging, (pure run control) is no longer sufficient.  Stopping the CPU in certain applications can cause mechanical damage. It can be hard to find bugs with the trigger condition more complex than the trigger resources, and the trigger condition occurs only after the unknown root cause of the error.

End of pipe quality assurance is too late to support a zero-defect culture and systems are too complex to rely on global debugging.Today’s world of complex systems with multi core, multi bus, multi thread, high clock rate SoC’s, needs something new.  On chip debug support at the core and system level is needed! The amount of traced data becomes too huge to get it off the chip without on-chip filter mechanisms. Trace memory has limited capacity.

The answer is Multi Core Debug Solution (MCDS). 

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The Freescale MPC5510 family is the first automotive 32-bit microcontroller, built on Power Architecture™ technology, featuring flexible low-power modes. This high-performance MCU inherits the single cycle access flash memory and advanced peripherals from the existing MPC5500 product families and reuses the same proven 130 nm automotive flash technology. The MPC5510 family is built on e200z0 and e200z1 core platforms, available through IPextreme, and is supported by outstanding development tools and software.

Freescale is continuing to lead the way in automotive solutions innovation, integrating a  Power Architecture™ e200 core with embedded flash memory and a FlexRay network controller onto a single chip. The MPC5567 MCU provides a powerful microcontroller with direct connectivity to a fault-tolerant, high bandwidth (10 Mbit/sec) FlexRay network, giving developers an unprecedented level of flexibility in their automotive designs.

Freescale has shipped over one million zero-defect 32-bit MCUs built on Power Architecture™ e200 cores.

To learn more about the IP available from IPextreme, please visit our website.