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CoReUse Core Store

CoReUse Educast Video

CoReUse™ is an enterprise class design reuse infrastructure from NXP Semiconductors that provides a proven framework for companies to develop and use semiconductor intellectual property. Developed and used at NXP over the last 10 years, CoReUse represents not only the industry’s leading example of IP reuse at work, but is a living and practical methodology that can adapt to changing technologies, standards, and EDA flows.

IPextreme is delivering the CoReUse standard to customers in three components:

  • A set of electronic books that customers can purchase under a low cost subscription license. E-books are available for online purchase from the Core Store
  • A Starter Kit package of training, templates and checklists that customers wishing to adopt CoReUse can use to quickly get started
  • A tool, QCore that engineers use to check the compliance of their IP against the CoReUse standard and produce certificates that provide an unbiased assessment of the IP quality and completeness
CoReUse E-Books

The CoReUse standard is captured in the form of electronic books organized into major volumes associated with different aspects of IP design and use. As CoReUse is a living standard, it is updated regularly with the latest best practices. The following CoReUse volumes are available on a per-user 1 year subscription model, with rights to any updates made during the subscription period. For volume discounts or group purchases please email us at core.store@ip-extreme.com.

CoReUse Foundation – $199

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These books are the heart of the CoReUse standard. They are offered as a set of companion books.

CoReUse Standards Book (170 pages)
This book describes the CoReUse standards for capturing and transferring the design views of reusable cores. It defines directory structure and file naming conventions. The required views for core deliveries are summarized in tables for digital blocks and analog/memory blocks. These standards define the details for CoReUse compliance levels 1 through 3.

CoReUse Constraints Reference Book (212 pages)
This document describes the CoReUse Constraints for IP design and core packaging. These are relevant for CoReUse Compliance Levels 4 through 6.

CoReUse Test and Debug – $50

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These books reflect the Test and Debug aspects of the CoReUse standard. They are offered as a set of companion books.

Test and Testability Flow for Packagers (27 pages)
This document describes what needs to be done in order to go from an IP block to a core, of which the test can easily be reused by integrators.

Test and Testability Flow for Integrators (24 pages)
This document defines what a core integrator should do to get core-based chips tested and explains what to expect from a core packager when ordering a core.

Core-based Scan Architecture for Silicon Debug (55 pages)
This document describes an architecture allowing a debug engineer to create state dumps of a digital chip via the IEEE Std. 1149.1-2001 Test Access Port (TAP), while the chip is in its intended application.

DfT Strategy for High Speed IO IP Blocks (38 pages)
This document describes the CoReUse standard DfT strategy for High-Speed I/O IP blocks.

Multi-TAP 2.0 Controller Architecture (42 pages)
This document describes an access architecture for a digital chips with multiple IEEE 1149.1 TAP controllers. This access architecture provides for compatibility with the 1149.1 standard as well as interoperability with other chips, boards, and production test systems using the JTAG standard.

CoReUse System Level Design – $50

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These books reflect the system level design aspects of the CoReUse standard. They are offered as a set of companion books.

Behavioral Synthesis (38 pages)
This document provides recommended standards and constraints for behavioral synthesis towards non-programmable cores using Cynthesizer from Forte Design Systems.

SystemC Transaction Level Modeling (34 pages)
This document outlines the CoReUse modeling methodology standard including the definition of abstraction levels and modeling styles. This document also covers the motivation for System Level Modeling, and an overview of use-cases.

Interrupt Architecture (50 pages)
This document specifies a generic Interrupt Architecture for use in Systems on Chip (SoC) built with one or more RISC or VLIW type processors and a multitude of interrupt request capable IP cores.

CoReUse CTAG Plug & Play Test Access – $50

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These books reflect an architecture and set of rules under the CoReUse standard associated with system level “plug and play” test. CTAG is currently under trial use and should be not considered a fully mature standard. They are offered as a set of companion books.

CTAG 1500 (96 pages)
This document describes the use of the IEEE Std 1500TM standard. Architecture choices have been made and standardized regarding the implementation of the architecture components of IEEE1500.

CTAG IP (38 pages)
This document specifies methods and solutions for testing core-based designs. Rules and guidelines are given concerning test data access and test control. All CTAG standards are being updated to adhere to the IEEE1500 Embedded Core Test Standard that was released in 2005. In IEEE1500 terminology CTAG.IP describes the standard for mergeable cores.

CTAG AMS Cookbook (50 pages)
This document specifies design for test methods and solutions for the problems of testing mixed-signal core-based designs. Rules and guidelines are given concerning mixed-signal design-for-test.

CTAG System (38 pages)
This document specifies methods and solutions for testing systems based on the concepts of testable IP. Rules and guidelines are given concerning the implementation and use of test ports and test access networks.

CoReUse Verification – $50

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These books reflect recommended verification practices under the CoReUse standard. They are offered as a set of companion books.

Assertion Based Verification (31 pages)
This document contains the CoReUse recommended practices for assertion-based verification and introduces associated verification concepts and benefits and shows related recommended CoReUse standards.

Test Bench Standard (33 pages)
This document describes a communication standard for stub reuse in IP and SoC testbenches. This standard enables IP providers to create stub components for off-chip interfaces in such a way that verification reuse is obtained for these interfaces.

Hardware Verification Software Standard (193 pages)
This document describes how the connectivity and interoperability of each individual IP core in an SoC or (sub-)system design can be verified by using software that runs on a processor that is also part of the same system. This software must be based on the API defined in this document. This leads to a VERIFICATION view of an IP that can be reused by the IP user to verify the system structure in which the IP is being embedded.

CoReUse Analog, Mixed Signal and RF – $50

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This book contains additional CoReUse standards and constraints for analog, mixed signal and RF designs.

Standards Book for Analog, Mixed Signal, and RF (78 pages)
This document describes the reuse standards for capturing and transferring the design views of reusable Analog, Mixed Signal and RF cores. It defines a directory structure and file naming convention for both the AMS and RF Design Environments. This version of the standards book defines the details for CoReUse compliance levels 1 through 3 for Analog, Mixed Signal and RF cores.

CoReUse AMBA – $50

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These books reflect recommended practices for using the AMBA™ on-chip bus system under the CoReUse standard. They are offered as a set of companion books.

AMBA Policy (14 pages)
This document discusses the policy for the application of AMBA buses at NXP Semiconductors to allow maximum re-use of IP functions across projects.

AHB/APB/VPB Naming Convention (12 pages)
This document contains the CoReUse recommended naming conventions for AMBA-based designs.

AXI Application Manual (56 pages)
This document describes how to use the AXI protocol in new SoC and IP designs. It describes the components to be found in an AXI subsystems and how to connect these. Integrators will find AXI specific details in this document that may help them in their design.