Core Store

CoReUse Foundation

CoReUse 4.6 Constraints Reference Book

The Constraints Reference Book provides sets of rules, guidelines, and hints to ensure that code is easily readable, follows good design practices, and is compatible with EDA tool flows. Adhering to these constraints ensures that your code is easy to reuse and easy to implement.

Price: $199.00

CoReUse 4.6 Standards Book

The Standards Book defines the standard set of deliverables for IP cores. It provides the framework to ensure that all required views of the core are available and that the files and directories associated with each view are correct and consistent. By adhering to the standards, you can be sure that users will easily locate the files they need and that task automation runs smoothly.

CoReUse Test and Debug

CoReUse 4.5 Multi-TAP 2.0 Controller Architecture

This document describes an access architecture for a digital chips with multiple IEEE 1149.1 TAP controllers. This access architecture provides for compatibility with the 1149.1 standard as well as interoperability with other chips, boards, and production test systems using the JTAG standard.

Price: $50.00

CoReUse 4.4.1 DFT Strategy for HSIO IP Blocks

This document describes the CoReUse standard DfT strategy for High-Speed I/O IP blocks.

CoReUse 4.4 Test and Testability Flow for Packagers

This document describes what needs to be done in order to go from an IP block to a core, of which the test can easily be reused by integrators.

CoReUse 4.4 Test and Testability Flow for Integrators

This document defines what a core integrator should do to get core-based chips tested and explains what to expect from a core packager when ordering a core.

CoReUse 4.1 Core-Based Scan Architecture for Silicon Debug

This document describes an architecture allowing a debug engineer to create state dumps of a digital chip via the IEEE Std. 1149.1-2001 Test Access Port (TAP), while the chip is in its intended application.

CoReUse System Level Design

CoReUse 4.6 SystemC Transaction Level Modeling

This document outlines the CoReUse modeling methodology standard including the definition of abstraction levels and modeling styles. This document also covers the motivation for System Level Modeling, and an overview of use-cases.

Price: $50.00

CoReUse 4.5 Interrupt Architecture

This document specifies a generic Interrupt Architecture for use in Systems on Chip (SoC) built with one or more RISC or VLIW type processors and a multitude of interrupt request capable IP cores.

CoReUse 4.5 Behavioral Synthesis

This document provides recommended standards and constraints for behavioral synthesis towards non-programmable cores using Cynthesizer from Forte Design Systems.

CoReUse CTAG Plug & Play Test Access

CoReUse 4.6 CTAG.1500

This document describes the use of the IEEE Std 1500TM standard. Architecture choices have been made and standardized regarding the implementation of the architecture components of IEEE1500.

Price: $50.00

CoReUse 4.5 CTAG.System

This document specifies methods and solutions for testing systems based on the concepts of testable IP. Rules and guidelines are given concerning the implementation and use of test ports and test access networks.

CoReUse 4.5 CTAG.IP

This document specifies methods and solutions for testing core-based designs. Rules and guidelines are given concerning test data access and test control. All CTAG standards are being updated to adhere to the IEEE1500 Embedded Core Test Standard that was released in 2005. In IEEE1500 terminology CTAG.IP describes the standard for mergeable cores.

CoReUse 4.5 CTAG.AMS Cookbook

This document specifies design for test methods and solutions for the problems of testing mixed-signal core-based designs. Rules and guidelines are given concerning mixed-signal design-for-test.

CoReUse Verification

CoReUse 4.5 Assertion Based Verification

This document contains the CoReUse recommended practices for assertion-based verification and introduces associated verification concepts and benefits and shows related recommended CoReUse standards.

Price: $50.00

CoReUse 4.6 Hardware Verification Software Standard

This document describes how the connectivity and interoperability of each individual IP core in an SoC or (sub-)system design can be verified by using software that runs on a processor that is also part of the same system. This software must be based on the API defined in this document. This leads to a VERIFICATION view of an IP that can be reused by the IP user to verify the system structure in which the IP is being embedded.

CoReUse 4.5 Testbench Standard

This document describes a communication standard for stub reuse in IP and SoC testbenches. This standard enables IP providers to create stub components for off-chip interfaces in such a way that verification reuse is obtained for these interfaces.

CoReUse AMBA

CoReUse 4.4 AXI Applications Manual

This document describes how to use the AXI protocol in new SoC and IP designs. It describes the components to be found in an AXI subsystems and how to connect these. Integrators will find AXI specific details in this document that may help them in their design.

Price: $50.00

CoReUse 3.2 AHB/APB/VPB Naming Conventions

This document contains the CoReUse recommended naming conventions for AMBA-based designs.

CoReUse 4.2 AMBA Policy

This document discusses the policy for the application of AMBA buses at NXP Semiconductors to allow maximum re-use of IP functions across projects.

CoReUse 4.6 Analog, Mixed Signal and RF Standards Book

This document describes the reuse standards for capturing and transferring the design views of reusable Analog, Mixed Signal and RF cores. It defines a directory structure and file naming convention for both the AMS and RF Design Environments. This version of the standards book defines the details for CoReUse compliance levels 1 through 3 for Analog, Mixed Signal and RF cores.

Price: $50.00