Cypress Semiconductor USB20Hub

Cypress Semiconductor, the market leader in USB, provides both the highest performance and lowest cost/lowest power USB 2.0 high-speed hub chips available today. And now the same design used in the Cypress EZ-USB HX2LP family of hub chips is available as synthesizable intellectual property (IP) from IPextreme.

You can configure the USB20Hub to match the different architectural options provided by variants of the EZ-USB HX2LP family of hub chips. In particular, you can implement 2–7 downstream ports and select your preferred transaction translator organization.

USB hubs often connect a mix of fast and slow USB devices; transaction translators (TTs) enable the hub to operate at the fastest speed available for each connected device. You can configure the USB20Hub to implement either:

Single TT for a smaller, lower cost design.
Multiple TTs to provide all of the 12-Mbit/s full-speed bandwidth to each full-speed downstream port

KEYS TO ARCHITECTURAL FIT AND MINIMUM RISK
Your Design Requirements	Met by USB20Hub through
Minimum chip area	Single-TT configuration minimizes chip area and cost
Maximum throughput to downstream devices	Multi-TT configuration provides full 12 Mbit/s to each downstream port
Functionally correct design	Production-proven silicon, USB certification, WHQL compliance
Rapid integration and implementation	Fully synthesizable design, EDA-neutral packaging ensures compatibility with your design tools

Several additional options are available through design parameters, input pins, and EEPROM, providing for both hardware design configuration and programmable in-system configuration.

Single-TT: One transaction translator shared between downstream ports

Multi-TT: One transaction translator per downstream port

FEATURES

Compliant to Universal Serial Bus Specification, Revision 2.0
USB-IF Certified: TID# 30000009
Silicon-proven design used in production USB 2.0 hub chips from
Cypress Semiconductor
Windows Hardware Quality Lab (WHQL) compliance proven in Cypress
devices
Supports high/full-speed upstream
Supports high/full/low-speed downstream
Fully synthesizable, technology-independent design; no firmware required
EDA tool-neutral packaging
No device-specific driver software required
Supports bus-powered or self-powered operation with dynamic switching between bus- and self-powered operation
Power control signals available to external clock control logic for reduced power operation
Configurable string descriptors with multiple language support
Supports in-system EEPROM programming

CONFIGURABILITY

Hardware implementation parameters determine:

Number of downstream ports (2–7)
Single-TT or multi-TT implementation
Default descriptor contents
Overcurrent detection timing
Indicator modulation control

Input pins control:

Port indicator polarity and activation
Overcurrent detection and polarity of overcurrent signalling
High-speed or full-speed
Single-TT or multi-TT
Ganged or individual power switching
Self-powerable status
Descriptor values (overriding default values as applicable)

Interface to external ROM/EEPROM for:

Descriptor values (overriding parameters/pins as applicable)
Active/removable port control
Power/overcurrent polarity control
Vendor-specific commands available to read/write EEPROM

APPLICATIONS

Suitable for all USB 2.0 hub applications, including:

Standalone hubs
Motherboard hubs
Monitor hubs
Advanced port replicators
Docking stations
External personal storage drives
Keyboard hubs

DELIVERABLES

Synthesizable Verilog source code
Integration testbench
Documentation
IPextreme XPack packaging technology for design configuration, simulation, and synthesis with support for common EDA tools

For more information about USB20hub, please conatct us at info@ip-extreme.com.