Test and Debug
The Compact JTAG IP implements the IEEE-1149.7 test and debug standard. Endorsed by both MIPI and Nexus5001, Compact JTAG builds upon traditional IEEE 1149.1 (JTAG) boundary scan to provide an enhanced test and debug standard that meets the demands of today’s complex chip designs. cJTAG offers test, debug and instrumentation utilizing only 2 pins (saving 4–6 pins), provides more capabilities than its predecessor 1149.1 JTAG, and maintains full compatibility with existing IEEE 1149.1-based hardware and software.
The DTS Adapter enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the advanced debug/test capabilities available with today’s IEEE 1149.7-enabled semiconductor devices, such as those that use the Compact JTAG IP.