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FRCC2100 – Freescale™ FlexRay™ Communication Controller

Freescale FlexRay PDF Brochure

FlexRay White paper

The FRCC2100 is the FlexRay Communication Controller synthesizable IP core from Freescale Semiconductor, the world’s leading supplier of semiconductor devices for the automotive industry. A founding member of the FlexRay Consortium, Freescale produced the first automotive-qualified FlexRay controller devices and provided the FlexRay controller IP for the first production vehicle to feature FlexRay technology—the BMW X5.

The FRCC2100 fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specification-defined Controller Host Interface (CHI) and Protocol Engine (PE) functionality, with clean partitioning between the CHI and PE functional blocks.

The FRCC2100 supports 4–252 message buffers and features standard interfaces to system logic and memories, so it can be readily optimized to your system requirements and easily integrated into your FPGA or ASIC device.

The host CPU interface is similar to the AMBA 2 APB. Example glue logic to connect to AMBA 2 APB is included with the product. The interface to FlexRay memory, which stores the message buffer header, payload, and status, is AMBA 2 AHB and can be adapted to other system memory interfaces upon request.

A rich ecosystem, including support from leading FlexRay software providers and a starter kit available for evaluation and prototyping, enables rapid software development.

System-on-Chip with FlexRay IP

FRCC2100 Key Features:

  • FlexRay Communications System Protocol Specification, Version 2.1, Revision A compliant protocol implementation
  • FlexRay Communications System Electrical Physical Layer Specification, Version 2.1, Revision A compliant bus driver interface
  • TUV conformance tested
  • Proven in Freescale's MFR43xx and MCP55xx devices
  • Dual or single channel support
  • Supports multiple FlexRay bus data rates: 10, 8, 5, and 2.5 Mbit/s (software selectable)
  • Number of message buffers supported is a hardware configuration option (4-252)
  • Number of message buffers used is a runtime option
  • Two independent message buffer groups with runtime-configurable payload size (0-254 bytes)
  • Each message buffer supports individual frame ID, channel ID, and cycle count filtering
  • Each message buffer can be configured for transmit or receive
  • Two transmit message buffers can be combined to form a double-buffered transmit message buffer
  • Transmit message buffers can be configured for state or event triggered transmission
  • Zero padding for transmit message buffers in static segment-applied when the frame payload length exceeds the size of the message buffer data section
  • Message buffers can be safely disabled and reconfigured
  • Message buffer header, status, and payload data stored in FlexRay memory
    • Flexible and efficient message buffer implementation
    • Buffer locking scheme ensures consistent data access
  • Two independent receive FIFOs
    • One receive FIFO per channel
    • Up to 255 entries for each FIFO
    • Global frame ID filtering
    • Global channel ID filtering
    • Global message ID filtering for the dynamic segment
  • Four configurable slot error counters
  • Four dedicated slot status indicators-used to observe slots without using receive message buffers
  • Clock synchronization data available to host system
  • Maskable interrupt sources-individual and combined
  • Two timers: 1 absolute, 1 absolute or relative
  • Strobe ports for visibility of selected internal signals
  • Separate clocks for CHI and PE
    • PE clock is 40 MHz (independent of configuration)
    • Minimum CHI frequency depends on number of message buffers
    • Clock Domain Crosser (CDC) block transfers signals between clock domains
  • Extensive clock gating for low power consumption

HARDWARE CONFIGURATION OPTIONS

OPTION
RANGE
DEFAULT
Maximum number of message buffers
4-252
32
FlexRay memory (AHB) data bus width
32 or 64 (bits)
32

GATE COUNT AND PERFORMANCE

NUMBER OF MESSAGE BUFFERS
GATES
MIN. CHI FREQUENCY
4
76,720
20
32
83,431
22
252
140,997
135

FRCC2100 IP ECOSYSTEM

  • FRCC2100 is supported by most FlexRay software providers for application, operating system, FlexRay stack, and driver software
  • FRCC2100 connects to FlexRay-compliant bus drivers

FRCC2100 PROTOTYPING/EVALUATION

MFR4310 FlexRay Starter Kit includes:

  • 2 FlexRay nodes (FRCC2100 in the S12XF chip)
  • CodeWarrior Development Tool CD with demonstration application, FlexRay monitor software, low-level drivers (unified driver written in C), and application examples
  • FlexRay stack software from Elektrobit (formerly DECOMSYS)

FRCC2100 DELIVERABLES

  • Synthesizable Verilog source code
  • Integration testbench and tests
  • Documentation
  • Automatic configuration through the IPextreme IP distribution and support portal
  • Scripts for simulation and synthesis with support for common EDA tools

For more product information, please contact core.store@ip-extreme.com.