Freescale FlexRay Communications Controller Core

To deliver the safety, comfort and entertainment features consumers are demanding, modern vehicles have become rolling data centers. With backing by almost all the leading car manufacturers and their electronics suppliers, FlexRay will shortly be the next widely implemented vehicle network standard. It delivers previously mutually exclusive functionality; being fast and flexible without giving up the reliability or deterministic behavior required by safety critical applications such as brake-by-wire.

Freescale Semiconductor is a founding and core member of the FlexRay Consortium and the world's largest supplier of automotive chips. With their immense automotive electronics knowledge and experience, Freescale was the first company to ship FlexRay standard parts in volume. Now that same FlexRay Communications Controller design proven in those chips is available as licensable intellectual property (IP) through IPextreme®.

As shown in the following table, attributes of the automotive industry drive several strict requirements in vehicle electronics that IP solutions best meet.

Automotive Requirements	Benefit of IP Integration
Automotive volume calls for low cost solutions	Integration reduces cost
Safety and customer satisfaction demands reliability	Integration reduces part counts and failure points
Limited cooling options and vehicle power budgets require minimal power consumption	Integration reduces power consumption and cooling requirements
Space limitations require small solutions, especially sensors	Integration reduces component size
Market viability demands absolute compatibility	Ensured by using the same design proven in the chips from the market leader

System-on-Chip with FlexRay IP

FRCC2100 Key Features:

Low power consumption through extensive clock gating
Modular design with clean CHI-PE interface for those who want to customize or develop their own Control Host Interface
CHI clock independent of PE clock through Clock Domain Crossing, which can be removed to reduce gate count
Compliant to FlexRay Communications Spec version 2.1A
Single 10Mbit/s channel for affordability, dual independent channels for 20Mbit/s, or redundant 10-Mbit/s channels for reliability
Data exchange (eg message buffer header, status & payload) through unified or standalone shared memory
Static message slots without buffer observable by host for debug
Maskable interrupt signals, individual and combined
Reports on clock synchronization
Straightforward interface to host CPU
One absolute timer and another absolute or relative timer
Easily configured to best suit your application, options include:
- Number of message buffers implemented is a hardware configuration option (4-256)
- Message buffer setup is programmed at runtime: number of message buffers used, payload size, transmit or receive
- Two independent receive FIFOs each with up to 255 entries and flexible filtering
- Four configurable slot error counters

FRCC2100 IP Deliverables:

Verilog RTL code of FlexRay module
ROM image for Protocol Engine microsequencer (Motorola S-record)
Integration testbench including:
- 3 node FlexRay cluster communication example
- Memory simulation models (DPRAM, SRAM, ROM)
- Bus Driver simulation model
- Clock and Reset Control
- Host bus functional model
- Bus Master Interface with interface to DPRAM
- Configuration setup example
- FlexRay bus sniffer
XPack™ IP Configuration GUI to specify options and timing and automatically generate synthesis scripts and constraints
EDA Neutral XPack packaging environment, supporting:
- Incisive, Modelsim, and VCS-MX for verification
- Design Compiler, RTL Compiler, BuildGates and Precision FPGA for Synthesis
- Documentation: XPack Guide, Integration Guide and User Guide

Silicon Proven in the MFR4200 and 4300
chip chip dye

The Customer Experience

The IPextreme engineering team has been creating quality IP for a decade, such as the first fully synthesizable ARM processor, the Infineon C166S, MPEG decoders and Bluetooth. Our engineers understand integration challenges and so rework and package the design for maximum ease of use. They will typically limit parameters to those most important, simplify interfaces, bundle software, supply suites that verify connectivity, and to generally transfer just the necessary knowledge from the original designers.

All the IP we ship is packaged in our patent pending XPack, which maximizes ease of use by letting the integration engineers configure complex IP through an intelligent user interface that outputs the configuration and constraints files for common tools from Cadence, Mentor and Synopsys. During the preparation and packaging of the IP, our engineers learn enough about it to offer excellent support. IPextreme takes advantage of professional commercial IP delivery software systems and our engineers stick with the customer to ensure they successfully integrate IP purchased from us.