Freescale V1 ColdFire Processor Core Core Store

Freescale V1 ColdFire Brochure

Flexis™ family controllers from Freescale Semiconductor, the world’s leading provider of 32-bit embedded controllers, provide the link between 8-bit ease-of-use and 32-bit performance. Freescale’s pair of pin-compatible controllers—the 8-bit S08QE128 and 32-bit V1 ColdFire based MCF51QE128—are the industry’s first fully compatible 8-bit and 32-bit architectures, sharing a common set of peripherals and development tools.

Fully compatible with the V2, V3, and V4 ColdFire architectures as well as the 8-bit S08 architecture, V1 ColdFire provides an entry point to the popular 32-bit ColdFire processor continuum. And now the same V1 ColdFire Core implemented in the MCF51QE128 is available from IPextreme.

The V1 ColdFire Core offers a low-cost entry point to the ColdFire roadmap. A simplified version of the V2 ColdFire architecture, the V1 ColdFire Core is a low-power, low-gate-count implementation with a single-wire debug interface.  Integration cost is minimized by simple interfaces to on-chip logic: unified instruction/data bus, interrupt, clock, and reset.

Debug support including trace and real-time debug (RTD) is through a single-wire background debug module (BDM) interface. The debug unit includes an embedded trace buffer with data compression for efficient storage and transfer of trace data. A separate debug clock enables shut-down of debug logic when not in use.

The V1 ColdFire instruction set includes special MAC/DIV instructions executed in dedicated MAC/DIV hardware. It also provides improved handling of byte (8-bit) and word (16-bit) operands and offers upward compatibity with other ColdFire cores such as the V2.

A rich ecosystem, including Freescale’s CodeWarrior integrated development environment, enable rapid software development and reuse of existing code.

The instruction fetch and execution pipelines are decoupled by an instruction buffer. Instructions can be fetched in advance, thereby minimizing stalls and accelerating throughput.

FEATURES
  • 32-bit processor core with 24-bit address bus
  • Unified instruction/data bus (AMBA 2 AHB)
  • Single-wire debug interface
  • Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
  • Independent, decoupled pipelines
    • 2-stage Instruction Fetch Pipeline (IFP)
    • 2-stage Operand Execution Pipeline (OEP)
    • FIFO Instruction Buffer is the decoupling mechanism
  • ColdFire Instruction Set Architecture Rev. C (ISA_C)
  • Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
  • Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
  • Static branch prediction mechanisms minimize change-of-flow execution time
  • Execute engines include ALU, barrel shifter, integer divider (DIV), and multiply-accumulate unit (MAC)
  • Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
  • Clock gating for reduced power dissipation
DEBUG SUPPORT

V1 ColdFire debug features include:

  • ColdFire Debug B+ functionality mapped into the single-pin BDM interface
  • 64x6-bit trace buffer provides programmable start/stop recording conditions plus support for continuous or PC-profiling modes
  • Capture of compressed processor status and debug data into trace buffer provides program trace capabilities
  • Compression of trace data enables capture of 500-1000 cycles of program trace in 64x6-bit trace buffer
  • Real time debug support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
  • Debug resources are accessible through the single-pin BDM interface or the privileged WDEBUG instruction from the core
  • Debug unit can use core clock (internally divided by 2) or a separate asynchronous clock
  • Separate clocks for processor and debug unit enable shutdown of debug unit when not in use
ECOSYSTEM

The entire ColdFire Family, including the V1 ColdFire Core, is supported by world-class development tools suites offered through leading tools developers including Freescale, Green Hills Software, Wind River Systems, Accelerated Technology/Mentor Graphics, and many others. Freescale’s CodeWarrior development tools offer a simple migration path from S08 to V1 ColdFire.

Also supported are a rich set of real time operating systems, stacks, and drivers from Freescale partners. For more information, go to www.freescale.com.

GATE COUNT AND PERFORMANCE

Gate count and maximum frequency depend on synthesis tool and target technology. Example values for a typical 130-nm technology are:

  • 46K (NAND2 equivalent) gates
  • 150 MHz (APB clock)
DELIVERABLES

The V1 ColdFire Core is delivered in encrypted Verilog and includes:

  • Synthesizable Verilog source code (encrypted)
  • Integration testbench and tests
  • Documentation
  • Scripts for simulation and synthesis with support for common EDA tools

For more product information, please contact core.store@ip-extreme.com.