CFV1CORE_ALTERA Core Store

Freescale V1 ColdFire for Altera Brochure

The CFV1CORE_ALTERA, available free-of-charge from IPextreme, is the same V1 ColdFire® processor core implemented in Freescale’s MCF51QExx devices, but delivered to you as an SOPC Builder ready design optimized for the Altera Cyclone® III FPGA. The V1 ColdFire system bus has been adapted to the Altera Avalon system interface for the CFV1CORE_ALTERA implementation. However, there are no architectural changes from the standard V1 ColdFire Core, which means the CFV1CORE_ALTERA fully supports the V1 ColdFire Instuction Set Architecture (ISA_C) and is code-compatible with existing V1 ColdFire devices.

The CFV1CORE_ALTERA IP that you receive from IPextreme is fully compatible with Altera’s SOPC Builder and Quartus II tools. That means you can quickly and easily build a system from the CFV1CORE_ALTERA and your selected peripheral IP blocks, then generate a bitfile of the whole system and program it onto your Cyclone III device. You can then download software through the V1 ColdFire single-pin debug interface and start running your application.

A free ColdFire processor on a low-cost, low-power Cyclone III FPGA gives you an ideal solution for both prototyping and production. And, should you want to migrate to an ASIC implementation in the future, you can get the same V1 ColdFire Core from IPextreme as fully-synthesizable RTL source code.

RESROUCES FOR HW/SW DEVELOPMENT

IPextreme provides the CFV1CORE_ALTERA, while resources from Altera and Freescale give you a jumpstart on hardware and software development.

Hardware development resources from Altera:

  • A rich library of peripheral IP blocks
  • V1 ColdFire-based hardware reference design
  • SOPC Builder for drag-and-drop IP selection and integration
  • Quartus II for synthesis, place-and-route, and device programming
  • Cyclone III FPGAs—low-cost 65-nm FPGAs

V1 ColdFire reference board from Freescale :

  • Evaluation/development board similar to Altera’s Nios II embedded evaluation kit, but containing the V1 ColdFire-based hardware reference design and equipped with a ColdFire debug connector
  • CodeWarrior development tools
  • Board support package
  • Software reference design

l

 

 

FEATURES

The V1 ColdFire Core offers a low-cost entry point to the ColdFire architecture. A simplified version of the V2 ColdFire Core, the V1 ColdFire Core is a low-power, low-area implementation that is fully upward compatible to higher-end ColdFire implementations such V2, V3, and V4.

Features of the V1 ColdFire Core as implemented in the CFV1CORE_ALTERA include:

  • 32-bit processor core with 24-bit address bus (upper 8 bits of 32-bit Avalon address bus are 0x00)
  • Unified instruction/data bus
  • Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
  • Independent, decoupled pipelines
    • 2-stage Instruction Fetch Pipeline (IFP)
    • 2-stage Operand Execution Pipeline (OEP)
    • FIFO Instruction Buffer is the decoupling mechanism
  • ColdFire Instruction Set Architecture Rev. C (ISA_C)
  • Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
  • Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
  • Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
  • Static branch prediction mechanisms minimize change-of-flow execution time
  • Execute engines include ALU and barrel shifter
  • Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
  • ColdFire Debug B+ functionality mapped into the single-pin background debug module (BDM) interface
  • Real time debug (RTD) support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)

In comparison to the configurable V1 ColdFire Core for ASIC implementation, the CFV1CORE_ALTERA is available in a single fixed configuration:

  • The hardware divider (DIV) and multiply-accumulate (MAC) unit are not included
  • The single-pin debug module is included but the 64-entry trace buffer is not, which means program trace is not supported
ECOSYSTEM

Like all ColdFire devices, the CFV1CORE_ALTERA is supported by a rich ecosystem of development tools, software stacks, and drivers from Freescale and other leading providers such as GNU, Green Hills Software, Wind River Systems, Accelerated Technology/Mentor Graphics, and many others.

TECHNICAL SPECIFICATIONS
  • Size ~6000 LEs
  • Frequency: 80 MHz (typical )
DELIVERABLES
  • Encrypted RTL source code and SOPC component for the CFV1CORE_ALTERA
  • Quartus IP license
  • Integration testbench and example test programs
  • Documentation